1. Field of the Invention
The present invention relates to a semiconductor device having a plurality of kinds of operation contents and, particularly, to a configuration for setting a test mode of the semiconductor memory device. More particularly, the present invention relates to a configuration for a test mode entry for setting a test mode of a semiconductor memory device and, specifically, to a configuration for a test mode entry of a pseudo SRAM which operates similarly to an SRAM (Static Random Access Memory).
2. Description of the Background Art
In an application of a portable equipment, an SRAM is used as an internal memory because of its high processing speed and simple control. The memory cell of the SRAM is, however, constructed by four transistors and two load elements. Consequently, the occupying area of SRAM memory cell is large, and it is difficult to implement a memory of a large storage capacity in a limited area.
As the functions of a portable equipment are enhanced, it is necessary to process data of a larger amount such as image data and audio data. A memory of a large storage capacity is required for a memory device of the portable equipment. In the case of using an SRAM, it is difficult to implement the memory of the large storage capacity in a small occupying area, so that a demand of down sizing and lightening of high-function portable equipment cannot be met.
On the other hand, the memory cell of a dynamic random access memory (DRAM) is constructed of one transistor and one capacitor. The DRAM has therefore an advantage that the occupying area of the memory cell is smaller, as compared to the memory cell of the SRAM. The DRAM can be said to be suitable for constructing a memory of a large storage capacity with a small occupying area. The DRAM has a further advantage that the occupying area of the memory cell is smaller and a cost per bit is lower as compared with an SRAM.
However, since the DRAM stores data in the capacitor, in order to prevent the stored data from being lost by a leak current, refreshing operation for rewriting data has to be periodically performed. During execution of the refreshing operation, an external device such as a processor cannot access the DRAM and has to wait, so that the processing efficiency of the system deteriorates. There is another problem that the load for the refreshing control of an external memory controller is heavy.
The DRAM is held in a standby mode such as a sleep mode in a waiting time in a portable equipment or the like. Also in such a standby mode, however, stored data has to be held and refreshing has to be executed periodically. Therefore, an ultra low standby current condition of the order of xcexcA required in a specification or the like for an operation period for holding data such as a sleep mode cannot be satisfied.
In order to implement the memory of a large storage capacity with the small occupying area at low cost, a DRAM-based memory has to be used. In the case of using such a DRAM-based memory, called an SRAM alternative memory hereinbelow, the memory replacement has to be done without significantly changing a conventional system configuration. In other words, compatibility of pins is required. The xe2x80x9cmemoryxe2x80x9d indicates a memory device connected to a device such as an external processor via pin terminals.
The SRAM alternative memory is required to operate under the same operating conditions, or the same signal timings, as those of the SRAM.
In the case of fabricating the SRAM alternative memory, in order to assure the reliability, a product test has to be sufficiently performed. In the case of using a DRAM-based memory, however, different from a conventional DRAM, for the operation control signals, a chip enable signal CE#, a write enable signal WE#, and an output enable signal OE# have to be used in view of compatibility with an SRAM. Therefore, the configuration of using signals RAS, CAS, and WE to set a test mode in a conventional DRAM mode cannot be used.
In the case of designating a special operation mode of the SRAM alternative memory as well, similarly, a mode setting condition used in a conventional DRAM cannot be used as it is. In the SRAM alternative memory, a new configuration has to be provided to designate a special mode such as a test mode. The configuration for designating a special mode has to be formed using an interface having compatibility with an interface of an SRAM.
An object of the present invention is to provide a configuration for designating a special operation mode of an SRAM alternative memory.
Another object of the present invention is to provide an SRAM alternative memory capable of designating a test mode while maintaining compatibility with an SRAM.
Further object of the present invention is to provide a semiconductor memory device that can reliably enter a test mode without exerting an adverse influence on a normal operation mode.
A semiconductor device according to the present invention includes: determining circuitry for determining whether an external signal satisfies a predetermined condition or not; and internal state setting circuitry enabled when a determination result of the determining circuitry indicates that the predetermined condition is satisfied, for setting, in accordance with an internal state designation signal designating a specific operation content, an internal state to a state designated by the internal state designation signal.
When the external signal satisfies the predetermined condition, a mode capable of setting a specific mode of operation is set, and the operation content in the specific mode is designated. By setting the predetermined condition in accordance with signals used in a normal SRAM, the specific mode can be designated while maintaining the compatibility with an SRAM.
An operation content is set in the specific mode only when the predetermined condition is satisfied, so that the operation content in the specific mode can be set accurately.
By constructing such that a predetermined condition is determined to be satisfied when a specific condition is met a plurality of times successively, a semiconductor device can enter a specific mode under the condition which is not used in a normal mode of operation. Consequently, the semiconductor memory device can be prevented from entering the specific mode erroneously in the normal mode of operation. Thus, highly reliable setting of a specific mode can be implemented.